The present invention relates generally to the packaging of integrated circuits. More particularly, the invention relates to leadless packaging designs and processes.
A leadless lead frame package (LLP) is an integrated circuit package design that contemplates the use of a lead frame in the formation of a chip scale package (CSP). The resulting packages are sometimes referred to as quad flat packsxe2x80x94no lead (QFN) packages. As illustrated in FIG. 1, in typical leadless lead frame packages, a copper lead frame strip or panel 101 is patterned (typically by stamping or etching) to define a plurality of arrays 103 of chip substrate features 105. Each chip substrate feature 105 includes a die attach pad 107 and a plurality of contacts 109 disposed about their associated die attach pad 107. Very fine tie bars 111 are often used to support the die attach pads 107 and contacts 109.
During assembly, dice are attached to the respective die attach pads and conventional wire bonding is used to electrically couple bond pads on each die to their associated contacts 109 on the lead frame strip 101. After the wire bonding, a plastic cap is molded over the top surface of the each array 103 of wire bonded dice. The dice are then singulated and tested using conventional sawing and testing techniques.
FIG. 2 illustrates a typical resulting leadless lead frame package. The die attach pad 107 supports a die 120 which is electrically connected to its associated contacts 109 by bonding wires 122. A plastic casing 125 encapsulates the die 120 and bonding wires 122 and fills the gaps between the die attach pad 107 and the contacts 109 thereby serving to hold the contacts in place. It should be appreciated that during singulation, the tie bars 111 are cut and therefore the only materials holding the contacts 109 in place is the molding material. The resulting packaged chip can then be surface mounted on a printed circuit board or other substrate using conventional techniques.
Since leadless lead frame packaging have proven to be a cost effective packaging arrangement, there are continuing efforts to provide further improvements to the package structure and/or processing to permit the package style to be used in additional applications and/or to improve specific characteristics of the resultant devices.
To achieve the foregoing and other objects and according to the purpose of the present invention, a variety of improved packaging arrangements are disclosed. A lead frame is patterned to define at least one array of device areas. Each device area has a plurality of contacts but no die attach pad. With this arrangement, the back surface of the die is exposed and coplanar with the exposed bottom surface of the contacts. A casing (e.g. encapsulating) material (which is typically plastic) holds the contacts and die in place. In one aspect of the invention, the back side of the die is metallized. The metallization forms a good attachment surface for the package and serves as a good thermal path from the die. In another aspect, the at least some of the contacts have a top surface, a shelf, and a bottom surface. The die is wire bonded (or otherwise electrically connected) to the shelf portions of the contacts.
The described package is quite versatile. In some embodiments, the top surfaces of the contacts are also left exposed which provides a very low profile device that is particularly well suited for stacking. A stack of LLP devices can thus readily be provided or other devices can be stacked on top of the described devices. Adjacent packages may be soldered together or otherwise electrically connected in any suitable manner.
In some embodiments, a heat sink is attached directly to the bottom surface of the die or package. This tends to provide a good thermal path from the die. In some embodiments, a recess or step is formed on the lower side of the contacts. This tends to improve the adhesion of the casing to the contacts.
In another aspect of the invention, a lead frame panel suitable for use in packaging these semiconductor devices is described. The lead frame panel includes at least one two dimensional array of the described device areas. A matrix of tie bars is provided that support the conductive contacts. The tie bars are arranged to define the two dimensional array of device areas with only the tie bars separating adjacent device areas within the two dimensional array. During assembly, an adhesive tape is adhered to the bottom surface of the lead frame panel and a plurality of dice are adhered to the adhesive tape. In a preferred embodiment, each die is positioned within an associated device area and electrically connected to the contacts of the associated device area via bonding wires that are wire bonded to the shelves of their associated contacts.
A plastic cap may be provided that covers the dice in an associated two-dimensional area of device areas. The cap encapsulates the bonding wires and provides mechanical support for the dice and the contacts such that when the adhesive tape is removed and the semiconductor devices are singulated, the corresponding plastic cap material holds each die and its associated contacts together leaving the bottom surfaces of the associated contacts and die exposed. In some embodiments, the plastic cap also leaves the top surfaces of the contacts exposed.
In other aspects of the invention, methods for packaging the described devices and for creating the described lead frame panels are disclosed.